The invention relates to a fabrication process for creating highly conductive P-buried layers in planar, silicon, epitaxial, monolithic, PN junction isolated integrated circuit (IC) devices. Such buried layers are desirably located under active circuit elements, such as PNP transistors, to reduce parasitic resistance. N-buried layers have been used for many years and their fabrication has become routine in connection with planar NPN transistors and other related elements. These employ either arsenic or antimony as donor doping elements which are useful because both are relatively slow diffusers in silicon when compared with phosphorous, the normal N dopant of choice. However, no P acceptor dopants have an equally slow diffusion as compared with boron which has a diffusion that roughly matches that of phosphorous. Accordingly, most PNP transistors incorporate a boron doped buried layer. Unfortunately, the relatively rapid diffusion of boron results in a relatively thick buried layer. This characteristic means that to produce suitably high voltage PNP transistors the epitaxial layer must be made substantially thicker than the equivalent layer for an NPN transistor. Furthermore, in IC devices wherein vertical NPN and PNP transistors are fabricated in the same process, as is set forth in U.S. Pat. Nos. 4,940,671 and 4,908,328, the epitaxial layer thickness must be a compromise. This makes it difficult to simultaneously optimize the performance of PNP and NPN transistors.
It would be very useful to employ a P-dopant that will produce the desired low resistivity layer and yet will not diffuse excessively into an overlying epitaxial layer.